Vhdl Program For Parity Generator And Parity

Anybody know how to code a parity generator in VHDL? Let's say for example a4-bit generator? Or some other even-bit generator?Use the following function frompackage stdlogicmisc:function XORREDUCE(ARG: STDLOGICVECTOR) return UX01;- Ben Cohen, Raytheon Systems, (310) 334-7389-. 'VHDL Coding Styles and Methodologies, 2nd Edition', Ben Cohen,- ISBN 0-7923-8474-1 Kluwer Academic Publishers, 1999-. 'VHDL Answers to Frequently Asked Questions, 2nd Edition',- Ben Cohen, ISBN 0-7923-8115-7 Kluwer Academic Publishers, 1998- Web page:Em03.03.99 00:00.

Wrote: Anybody know how to code a parity generator in VHDL? Let's say for example a 4-bit generator? Or some other even-bit generator? Any help would be great.

Odd Parity Generator- This module has two inputs, one output and one process.- The clock input and the inputstream are the two inputs. Whenever the clock- goes high then there is a loop which checks for the odd parity by using- the xor logic.There is package anu which is used to declare the port.

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Thanks, -Steven. you can send replies to this newgroup or to sbutts @Two alternative descriptions:- one uses the well known parity chain. An alternative to this descriptionis a process that contains a FOR LOOP with the XOR operation.- the second has a more behavioural view, it count the numbersof ones.Both result in the same logic (witjh my synthesis tool)Regards,Egbert MolenkampENTITY parity1 ISGENERIC (nbits: positive:= 3);PORT (d: IN bitvector(nbits-1 DOWNTO 0);odd: OUT bit;even: OUT bit);END parity1;ARCHITECTURE xorchain OF parity1 ISSIGNAL chain: bitvector (nbits DOWNTO 0);BEGINchain(nbits). Be careful of using a loop or function call. You do not know how it willsynthesize.

It may not matter as what you get may be fast enough. I tend tobuild my own parity function using parenthases to specify how I want the XORgates structured.

This way, I am more likely to get a balanced tree ratherthan a long chain:Good:ODDPARITY. Wrote: Be careful of using a loop or function call. You do not know how it will synthesize. It may not matter as what you get may be fast enough.

I tend to build my own parity function using parenthases to specify how I want the XOR gates structured. This way, I am more likely to get a balanced tree rather than a long chain: Good: ODDPARITY Not so good: ODDPARITY BTW, to get even parity, just add one, better yet, ODDPARITY = EVENPARITYN (not). One more thing, if you have more info on the library of the part you are targeting, you can better optimize the tree. For example, if your ASIC library contained a 3 input XOR gate (some do) then build your tree based on that: Eg. ODDPARITY Good Luck!

PJIs it naive to think that the syntheziser will also figure this out?I mean why should it make a chain if it can make a three, and I thinkit should atleast be smart enough to know how to make large logicfunctionsin 'chucks' that fit the technology-L2C-Lasse Langwadt Christensen, MSEE (to be in 1999)Aalborg University, Department of communication tech.Applied Signal Processing and Implementation (ASPI), mailto:philj.@my-dejanews.com04.03.99 00:00. Let's take Synopsys as an example. It uses a set of rules (constraints) tosynthesize. It scores each solution and uses the 'best' one. There is atrade-off between area and speed.

It typically uses the design that providesthe needed speed with the smallest area. However, for a parity function, atree and a chain both contain the same number of gates and nets, so which isbetter. The tree is faster but if the chain meets your speed requirement, itMAY be used instead of the tree.What will the tool do in a given situation I can't say for sure.

Not sureanyone can. I can say that I have done parity checkers and generators andSynopsys DID implement them as chains or poorly structured trees until Iadded the parenthesis to tell it exactly what I wanted.

Would what itgenerated have worked? Yes, because it met the speed requirement (and allother constraints). Is it what I wanted?

So, I changed it.Not trying to be difficult here, just trying to point out one of thesubtleties of synthesis.PJIn article,- Posted via Deja News, The Discussion Network -Search, Read, Discuss, or Start Your OwnEm05.03.99 00:00. Wrote: Be careful of using a loop or function call.

You do not know how it will synthesize. It may not matter as what you get may be fast enough. I tend to build my own parity function using parenthases to specify how I want the XOR gates structured.

This way, I am more likely to get a balanced tree rather than a long chain: Good: ODDPARITY Not so good: ODDPARITY - If you like a balanced tree like structure AND the number if inputs shouldstill- be generic! You could use the following VHDL description.- It is synthesisable (at least with my synthesis tool).- The solution is NOT mine!

(I don't remember the original author)- I only changed it a little to make it synthesiable. My synthesis tool- did not support an 'unconstrained' array in the port declaration, therefore- I added a GENERIC.- Original it was:- entity ParityTree is- port (Inputs: in BitVector;- Output: out Bit);- end ParityTree;- I replaced it with:- entity ParityTree is- generic (nmb: integer);- port (Inputs: in BitVector(1 TO nmb);- Output: out Bit);- end ParityTree;- Have FUN.- Egbert Molenkamp-This example is the VHDL implementation of:- 'To make an n-bit parity generator, take two n/2-bit parity generators- and connect their outputs with an xor gate. A one-bit parity generator- is a piece of wire.' Entity ParityTree isgeneric (nmb: integer);port (Inputs: in BitVector(1 TO nmb);Output: out Bit);end ParityTree;architecture Recursive of ParityTree iscomponent ParityTreegeneric (nmb: integer);port (Inputs: in BitVector (1 TO nmb);Output: out Bit);end component;alias MyInput: BitVector (1 TO Inputs'Length) IS Inputs;signal LowerHalfParity: Bit;signal UpperHalfParity: Bit;signal lower: bitvector(1 TO MyInput'Length/2);signal upper: bitvector(MyInput'Length/2 + 1 TO MyInput'Length);beginGeneralCase:if MyInput'Length 1 generatelower.

Phil jackson writes: What will the tool do in a given situation I can't say for sure. Not sure anyone can.

I can say that I have done parity checkers and generators and Synopsys DID implement them as chains or poorly structured trees until I added the parenthesis to tell it exactly what I wanted. Would what it generated have worked? Yes, because it met the speed requirement (and all other constraints). Is it what I wanted? So, I changed it.I'm curious.

Why did you want precise control over the tree structure,if Synopsys synthesised a working structure already?Is it that you did not/could not enter the real constraints for yourapplication?Curious,- JamieJamie Lokier12.03.99 00:00. I wrote: I'm curious. Why did you want precise control over the tree structure, if Synopsys synthesised a working structure already? Is it that you did not/could not enter the real constraints for your application?I ask because I am interested in techniques for synthesis, and whatreal-life designs require from it.In my mind, adding parantheses wuold not guarantee control over thesynthesised tree structure: just as the tool may convert 'a XOR b XOR cXOR d' into any shape it likes, it has the freedom to implement anythingthat is equivalent to '(a XOR b) XOR (c XOR d)'. That is, it maysynthesise a chain from the latter equation, although it may be lesslikely to find that as its first solution.- JamieRichard Guerin13.03.99 00:00.

This chapter explains the VHDL programming for Combinational Circuits. VHDL Code for a Half-AdderVHDL Code:Library ieee;use ieee.stdlogic1164.all;entity halfadder isport(a,b:in bit; sum,carry:out bit);end halfadder;architecture data of halfadder isbeginsum.